Semiconductor device manufacturing generally includes various steps of device patterning process. With continuous scale-down and shrinkage of real estate available for a single semiconductor device, engineers are daily facing the challenge of how to meet the arket demand for ever increasing device density. One technique was the creation of finFETs, which are formed through a technique called sidewall image transfer (SIT), also known as sidewall spacer image transfer. However, due to the scaling of these devices, there remains a risk of pattern collapse for tight pitch and high aspect ratio configurations, such as the fin or gate modules.